Microprocessor equipped with parity control unit on same chip.

摘要

A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data terminals and the execution unit, and the data bus buffer fetches data on the set of data terminals in response to a first timing signal and transfers the fetched data to the execution unit in response to a second timing signal. The on-chip redundant control unit receives the fetched data and redundant information and checks the validity of the fetched data in response to the redundant information before the generation of the second timing signal, so that an effective memory access time is not prolonged.