发明名称 PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To improve the degree of circuit integration by providing plural 1st fuses whose one side of terminals are connected to diodes connecting to real outputs of buffers caused among plural input buffers and plural 2nd fuses whose one side of terminals are connected to diodes connecting to complementary outputs of buffers caused among plural input buffers. CONSTITUTION:Suppose that an input to a terminal I0 is logic 0, the real output of an input buffer 35 is logic 0, a large current flows from a product term line P0 and a fuse 33 is blown. In this case, since the level of the complementary output is logic 1 (the same level as a high potential of the product term line P0), a fuse 34 is left as it is. Other prescribed fuse is blown relating to the product term line P0 similarly. A current is detoured to other product term lines relating to the product term line P0, then the current passes through two resistors and the current does not reach a value to blow fuses with respect to other product term lines and this is applied similarly to the product term line P1 and its succeeding lines. Thus, the manufacturing yield and the circuit integration are improved.
申请公布号 JPH01319329(A) 申请公布日期 1989.12.25
申请号 JP19880152806 申请日期 1988.06.20
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MATSUNO SHUNJI
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
主权项
地址