| 摘要 |
PURPOSE:To realize miniaturization at the time of making the transfer speed converter and the FIFO of data into integration by using a synchronous single port memory. CONSTITUTION:Serial data with a frequency (a) is stored in the single port memory 1. A serial-parallel converter 2 is operated with the frequency (a), and a parallel-serial converter 3 inputs the data of (n) bits outputted from the serial-parallel converter 2, and sets a flag 4. Furthermore, the data of (n) bits is outputted bit by bit sequentially with a frequency (b). A readout signal generating device 5 generates a pulse synchronized with a clock of frequency (a) only when the flag 4 is set, and an address generating device 6 sends a readout address to the memory 1 synchronizing with the output signal of the device 5. Also, to perform a write operation on the memory 1 with the frequency (a) and a readout operation with the frequency (a) alternately, it is performed by setting the frequency of the clock to be supplied to the memory 1 at 2a, that is a doubled frequency and performing read-in and write alternately. |
