| 摘要 |
A video signal processing circuitry which comprises a first arithmetic circuit adapted to receive a line sequential signal, a first 1H delay circuit for delaying an output from the first arithmetic circuit for a length of time equal to one horizontal period, a second 1H delay circuit for delaying an output from the first 1H delay circuit for a length of time equal to one horizontal period, a second arithmetic circuit adapted to receive the line sequential signal and the output from the second 1H delay circuit, a coefficient multiplier for varying the level of the output from the second arithmetic circuit according to a predetermined coefficient, an adder for summing the output from the first arithmetic circuit and the output from the second 1H delay circuit, a level control circuit for controlling the level of an output from the adder, and a switching device for sequentially providing an output from the level control circuit to first and second output terminals one for each horizontal period and also for sequentially providing the output from the first 1H delay circuit to the second and first output terminals one for each horizontal period.
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