| 摘要 |
<p>A multiprocessor control system adapted to a multiprocessor system includes a switching circuit (6, 25), a control stage circuit (4, 5, 7 - 9; 23, 24, 28 - 30), a switching mode setting circuit (11, 27), and a switching control circuit (10, 26). The switching circuit (6, 25) selectively switches the second group of instructions supplied from the first execution units to thereby select the second group of instructions relating to one of the plurality of first execution units. The control stage circuit (4, 5, 7 - 9; 23, 24, 28 - 30) includes a plurality of register stages used for controlling a pipeline process. The control stage circuit sequentially stores the second group of instructions relating to the selected one of the first execution units in the register stages and outputs, for every register stage, a state indicating signal indicating state information on the corresponding register stage. The switching mode setting circuit (11, 27) generates a mode setting signal used for selecting one of a plurality of switching modes (M1, M2, M3) each defining a timing with which the switching by the switching circuit is done. The switching control circuit (10, 26) generates the switching signal based on the state indicating signals output from the control stage circuit and the mode setting signal indicative of one of the plurality of switching modes supplied from the switching mode setting circuit.</p> |
