Circuit arrangement for the phase synchronisation of clock pulses

摘要

The circuit arrangement represents a phase control loop serving for the phase synchronisation of clock pulses, having a controllable clock oscillator (VCXO), a frequency divider (FT) connected downstream thereof and a phase discriminator (PLL). From this phase discriminator, the clock oscillator receives control signals fed via a low-pass filter, which permit phase control within a prescribed proportional range. Additionally, a control device (SE, SE') is provided for coarse phase synchronisation, which control device determines a phase deviation lying above a prescribed threshold and, in the presence of such a phase deviation, modifies the clock pulse train emitted by the clock oscillator in such a way, that additional clock pulses are inserted into this clock pulse train or clock pulses are removed from this clock pulse train, according to the amount of the phase deviation. <IMAGE>