| 摘要 |
PURPOSE:To prevent malfunction based on an abnormal mode, by setting an output of the 2nd stage FF to a specific state with a signal detecting the coincidence of the FF outputs of the 1st and the 3rd stage, in a hexad counter circuit comprising the three stages of FFs. CONSTITUTION:In the hexad counter circuit constituted with FFs 7-1-7-3 connected in cascade and by feeding back a Q' output of the FF7-3 to the FF7-1, the Q' output of the FF7-1 and the FF7-3 is inputted to an NAND circuit 8, and an output of the circuit 8 is inputted to a reset terminal R of the FF7-2. When the Q output of the FF7-1, 7-3 is both 0, the output of the circuit 8 is 0, the FF-2 is reset, and even if the circuit state is (010), the state is initially set to (000) forcedly. When the circuit state is (101), since it is (010) at the next step, the initial set is done in this state. Thus, the malfunction of the repetitive mode of (010) and (101) takes place, the circuit state is set to the initial set automatically. |
