| 摘要 |
The latch circuit includes a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, where the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side, which the feedback signal is between the peak voltage of the logic amplitude and the reference voltage at the side which the write data signal is applied.
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