| 摘要 |
<p>An interrupt control circuit (12) for a multi-master bus which receives interrupt requests from other modules via a multi-master bus (20), generates an interrupt vector number for an interrupt factor, and sends it to a CPU (22). The interrupt control circuit comprises a conventional first vector number generating circuit (18) as well as a second vector number generating circuit (16) which converts a first vector number (N1) generated by the first vector number generating circuit into a vector number (N2) that corresponds to the kind of interrupt when the first vector number (N1) is the one that corresponds to an external interrupt signal. It is therefore made possible to generate different vector numbers depending upon the kinds of interrupt factors from other modules, and whereby there is no need of determining the interrupt factor from the other modules that so far had to be carried out based on a software processing. Therefore, the software processing is reduced and, particularly, the overhead of the real time monitor is greatly reduced.</p> |
