发明名称 MALFUNCTION PREVENTING CIRCUIT
摘要 PURPOSE:To eliminate noise without causing the reduction in fan-out, reduction in the mount density and any cost-up by providing a delay circuit outputting plural delay signals and a logic circuit taking majority decision logic of plural delay signals and giving an output. CONSTITUTION:A delay circuit 10 gives delays of '0', t and t2 to a digital input signal to generate three delay signals. A logic circuit 12 takes majority decision logic of the three signals. For example, suppose that noise is superimposed on, e.g., a digital signal and the signal level is changed momentarily to a high level, then the high level is given to the logic circuit 12 as it is and delayed by t and t2 the result is given to the logic circuit 12. As a result, when one of inputs to the logic circuit 12 is at a high level, the other two inputs are at a low level without fail. Thus, the majority decision logic results in a low level. The noise is eliminated from the input signal as the output of the logic circuit 12.
申请公布号 JPH01295516(A) 申请公布日期 1989.11.29
申请号 JP19880125452 申请日期 1988.05.23
申请人 FUJITSU LTD 发明人 SUZUKI YASUAKI
分类号 H03K5/1252;H03K5/01 主分类号 H03K5/1252
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