Data demodulation apparatus.

摘要

A data demodulation apparatus applicable to a playback input signal from a digital recording apparatus, which executes A/D conversion of the input signal with a sampling period that is equal to the bit separation of that signal, and obtains phase data for reproducing the phase of the clock signal component of the input signal each time that a "1" state bit is detected in a sampling period. For each sampling period, or set of successive sampling periods, data values are derived which respectively represent a number of bit positions of the input signal within that period and the presence or absence of "1" state bits in the period, and these data values are converted to serial form to respectively constitute a reproduced clock signal and a detected data signal.