DIGITAL PLL CIRCUIT

摘要

PURPOSE:To prevent production of irregular hazard of a PLL circuit and to make the operation stable by giving a signal synchronizing an input signal with an output of a multiplexer to a phase comparator circuit and using the output so as to clear the 1st frequency divider circuit. CONSTITUTION:A high frequency signal from an FSK input signal is given to a multiplexer 2 via an inverter 11 and a 1/4 frequency divider circuit 1. If no clear signal is given from a clear circuit 12, a clock signal is subject to 1/4 frequency division and then fed to the multiplexer 2. The multiplexer 2 selects either input by using an output of an EOR circuit 4 and gives the result to a 1/32 frequency divider circuit 3 via an inverter 15. The FSK input signal is fed to an exclusive OR circuit 4 as a signal synchronously with the output of the multiplexer 2 by a flip-flop 16. Thus, then the FSK input signal and the output of the 1/32 frequency divider circuit 3 are synchronized at the trailing point of time of the multiplexer 2.