| 摘要 |
PURPOSE:To constitute a high speed digital PLL easily by a simple hardware by constituting a control pulse generator for a digital PLL and a control section not by a circuit depending on an input clock such as a counter but by a gate circuit and a selector only applying code processing independently of the input clock. CONSTITUTION:An output (d) of a protection circuit 6 is given to confirmation gates 43, 44 so as to confirm that an output C1 of a lead gate 31 of a control pulse generator 3 or an output C2 of a lag gate 32 is connected by a prescribed time only. Then a delay phase controller 41 is driven by using the output C2 of the lag gate 32 against the phase lag of a PLL output pulse Pfo to eliminate part of the pulse of the output Nf of a fixed oscillator section 2. Furthermore, a lead phase controller 42 is driven by using the output C1 of the lead gate 31 against the phase lag of a PLL output pulse Pfo to select an output MNf of the oscillator 21 of the fixed oscillator section 2 tentatively and to add prescribed number of pulses thereby obtaining a PLL output pulse Pfo phase-locked with the reference input pulse Pf. Thus, even if the digital signal to be handled is high in speed, the circuit constitution is simplified for speed up. |
