发明名称 INTERDIGITAL SIGNAL PROCESSOR DATA TRANSFER SYSTEM
摘要 <p>PURPOSE:To reduce the software load despite a large quantity of data and to realize the transfer of a large quantity of data by setting a memory means having the 1st and 2nd address at a position between the master-slave digital signal processors DSP which are used for a voice CODEC, etc. CONSTITUTION:For instance, the data are written into one of two address areas, e.g., a 1st address area of an adjacent memory means 500-1 from the master side in a prescribed period decided by a synchronizing signal. At the same time, the data are written into the other address area, e.g., a 2nd address area of the means 500-1 from a slave side digital signal processor 200-1. Then the data are read out of the 2nd address area of the means 500-1 at the master side in the next prescribed period decided by the synchronizing signal. While the data are read out of the 1st address area of the means 500-1 by the processor 200-1. Thus, it is possible to ensure the same effect as that obtained in a case where the data are transferred between the master side and the slave side 200-1 in a prescribed period.</p>
申请公布号 JPH01284958(A) 申请公布日期 1989.11.16
申请号 JP19880115506 申请日期 1988.05.12
申请人 FUJITSU LTD 发明人 ITO ATSUHIRO
分类号 G06F15/167;G06F13/38;G06F15/16 主分类号 G06F15/167
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