| 摘要 |
<p>PURPOSE:To reduce the power consumption in an HALT mode (mode for reducing the power consumption in a holding state) without decreasing an operation processing speed by providing an interruption commanding circuit which is started by a start signal which has been outputted from a processor, outputs an interrupting signal to the processor after a prescribed time and releases a low power consumption mode of the processor. CONSTITUTION:When an operation processing is all ended, a processor 1 outputs a start signal 6 and starts an interruption commanding circuit 2, and thereafter, becomes an HALT mode. After a prescribed time, the interruption commanding circuit 2 outputs an interrupting signal 5, and release the HALT mode of the processor 1. In such a way, the interruption can be controlled so that it is generated only at the time releasing the HALT mode, and it is not generated in the course of the operation processing, therefore, it does not occur that an operation processing speed of the processor 1 is decreased. Also, since the interruption commanding circuit 2 is constituted of an integration circuit, a current which is consumed in the interruption commanding circuit 2 is only a current for charging and discharging a capacitor of the integration circuit, and it does not occur that the power consumption the HALT mode increases.</p> |
