| 摘要 |
PURPOSE:To select a proper timing signal in response to the state of an opposite connected device by providing a supervisory means monitoring the 2nd timing signal from a data line terminator and selecting a transmission clock of a serial input/output interface in response to a monitor signal from the supervisory means. CONSTITUTION:A counter CT14 generates an internal clock having a frequency corresponding to the data transfer speed designated by a microprocessor 11. The internal clock is fed to one input of a selector SEL15. An ST2 clock from an opposite DCE is supplied to other input of the selector 15 via a driver/ receiver circuit 19. A supervisory timer 16 is set when the ST2 clock is received and reset when not received. The selector 15 selects the ST2 clock as a transmission clock used in an SIO12 when a output signal of the supervisory timer 16 is set and selects the internal clock from the counter 14 as the transmission clock when the timer 16 is reset. Thus, proper transmission in response to the state of an opposite DCE is attained. |
