发明名称 CLOCK INTERFACE CIRCUIT FOR TIME DIVISION MULTIPLEXER
摘要 <p>PURPOSE:To attain remote monitor from a remote location of a multiplex communication equipment by providing a clock out of synchronism detection circuit, a clock supply device operation monitor signal extraction circuit and a CPU bus interface circuit. CONSTITUTION:The clock interface circuit 4 of a time division multiplexer 2 is provided with a clock out of synchronism detection circuit 11 detecting out of synchronism between a clock from a line in the circuit and a clock from a clock supply device 5 and a clock supply device operation monitor signal extraction circuit 14 extracting the operation monitor signal of the clock supply device 5. Then a CPU bus interface circuit 15 to apply remote monitor to the output signal of both the circuits 11, 14 at a remote location via a CPU bus is provided. Thus, the operating state of the clock supply device is controlled remotely by the communication network management system comprising the time division multiplexer.</p>
申请公布号 JPH01273446(A) 申请公布日期 1989.11.01
申请号 JP19880101272 申请日期 1988.04.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 FUJITA KIYOSHI
分类号 H04J3/06;H04J3/14;H04L7/00 主分类号 H04J3/06
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