发明名称 MEMORY READING CIRCUIT
摘要 <p>PURPOSE:To obtain a memory reading circuit to stably read data by providing a precharge detecting circuit to detect large current supply to a bit line and a circuit to receive the detected signal of the precharge detecting circuit and temporarily hold a potential. CONSTITUTION:When bit lines 7 and 8 are switched, and large current is supplied from a sense circuit to the bit lines, a precharge detecting circuit 11 operates a holding circuit 12 between an output circuit 4 and an amplifying circuit 3, holds the data state of the output circuit 4, which is the one before the sense circuit supplies the large current, and simultaneously separates the amplifying circuit 3 and the output circuit 4. When the potentials of the bit lines 7 and 8 become higher, and the current supplied to the bit lines is reduced, the precharge detecting circuit 11 detects this, makes the holding circuit 12 into an OFF state, and links the amplifying circuit 3 and the output circuit 4. When the sense circuit is charged, the output circuit 4 is held and separated from a front step circuit, and when the charging of the sense circuit is completed, the holding is released, and the output circuit 4 is linked with the front step circuit. Thus, a meaningless deflection in the output circuit 4 can be suppressed, and the data can be read stably.</p>
申请公布号 JPH01271995(A) 申请公布日期 1989.10.31
申请号 JP19880099446 申请日期 1988.04.22
申请人 SEIKO EPSON CORP 发明人 UEMATSU AKIRA
分类号 G11C17/00;G11C7/00;G11C16/06 主分类号 G11C17/00
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