| 摘要 |
The circuit includes multiplexers (MUT1MUT8) for selecting and for multiplexing input data according to input selection signal (S/P), D- type flip-flops (FF1-FF8) for shifting output signals of multiplexers utilizing clock pulse, a latch unit (LAT) for latching data from flip-flops utilizing latch clock pulse (CLK), and buffers (B0-B8) for prohibiting collision of data from input terminals during conversion of serial or parallel data.
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