发明名称 PHASE CONTROL CIRCUIT
摘要 PURPOSE:To obtain a regenerated output with less jitter even if an input signal containing much jitter is inputted by inhibiting if a value that phase difference between an output signal and an input signal is integrated while the input signal is inputted M times is a leading phase, and not inhibiting if said value is a lagging phase. CONSTITUTION:The phase difference between the input signal and the output signal is integrated by an up-down counter 1 while the input signal is inputted M times, and if an integrated result output signal is leading, a 1, 0 signal generating part 11 outputs 1-level, and if lagging, it outputs 0-level, and a signal to be inputted to a rising differentiation circuit 9 is changed from the input signal so that the signal that the output signal is M-frequency divided by an M-frequency divider 2 is inputted, and the up-down counter 1 is cleared by the output of the differentiation circuit 9. Accordingly, the jitter comes to be the mean value during a period the input signal is inputted M times, and since phase control is performed one time when the input signal is inputted M times, the regenerated output with less jitter can be obtained even if much jitter is contained in the input signal.
申请公布号 JPH01269332(A) 申请公布日期 1989.10.26
申请号 JP19880098757 申请日期 1988.04.21
申请人 FUJITSU LTD 发明人 GOTODA TAKAO
分类号 H03L7/06;H04L7/02;H04L7/033 主分类号 H03L7/06
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