| 摘要 |
PURPOSE:To prevent an alarm of non-closure from being issued erroneously even when a clock from which a pulse is missed is inputted as an input signal by providing a pulse missing detection circuit, and prohibiting the detection of a non-closure state in case of missing the pulse of a PLL frame signal as being set at the zero state of an RZ signal. CONSTITUTION:The output LD of an AND circuit 8 is outputted when the phase difference of input/output signals of a PLL exceeds T seconds. Next, the input/output signals Pin and Pout of the PLL5 are inputted to an exclusive OR circuit 5 having the function of a phase comparator, and the output of the exclusive OR circuit 6 goes to a pulse signal LD' having width equivalent to the phase difference between the signals Pin and Pout. Also, the input signal Pin is delayed by T seconds by a delay circuit 9, and the output D of the delay circuit 9 and that of an AND circuit 7 are inputted to the AND circuit 8. Even when the Pin is missed like the zero state of the RZ signal at the time of establishing PLL phase-locking, no pulse representing the non-closure state is outputted when no phase difference between the input/output signals Pin and Pout of the PLL5 exceeds T seconds. |
