CIRCUITS FOR ACCESSING A VARIABLE WIDTH DATA BUS WITH A VARIABLE WIDTH DATA FIELD

摘要

A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width Nc and a data field of Nf, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field Nf extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo Nc combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit Nc. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.