| 摘要 |
An integrated CMOS circuit comprising a transistor (T2) located in a p (or an n) well (5) and an adjacent complementary transistor (T1). The transistors are located in an epitaxial layer (4) on a highly doped substrate (2). With the use, for example, in bridge circuits having an inductive load, parasitic currents can occur, which give rise to "latch-up" and/or dissipation. According to the invention, this can be avoided in that under the source zone of the transistor (T1) located beside the well is provided a second region having substantially the same doping and depth as the well, which is connected to the said source zone. |
