发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To adjust the clock frequency accurately in a short time by detecting a frequency error of an oscillated signal through the comparison between a reference clock and an oscillation signal, correcting the frequency division ratio of the oscillated signal by the frequency division circuit by the frequency error so as to allow the frequency division circuit to output a clock with a prescribed frequency. CONSTITUTION:A correcting circuit 7 receives an oscillation signal (a) outputted from an oscillating circuit 1 and a reference clock (c) having a known prescribed frequency received externally, compares the frequencies to detect the frequency error of the oscillated signal (a) from the comparison. The detected frequency error is stored in a storage circuit 8 comprising a nonvolatile memory, read for each application of power supply and supplied to the correction circuit 7. Then the correcting circuit 7 frequency-divides the oscillated signal (a) outputted from the oscillating circuit 1 by the frequency division ratio corrected in proportion to the quantity in response to the frequency error to output a clock (b) of a prescribed frequency. Thus, the clock frequency is adjusted accurately in a short time without operator intervention.</p>
申请公布号 JPH01261025(A) 申请公布日期 1989.10.18
申请号 JP19880089407 申请日期 1988.04.12
申请人 MITSUBISHI ELECTRIC CORP 发明人 NAONAGA YUKIHISA;OTANI KIMIKO
分类号 G04G3/02;G06F1/04;G06F1/14;H03K21/40 主分类号 G04G3/02
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