| 摘要 |
PURPOSE:To adjust the delay time of a clock in the unit of a delay time equivalent to that of a logic element in an LSI by providing an inter-LSI clock skew adjustment circuit in the inside of each LSl. CONSTITUTION:The clock skew between two LSls 11a and 11b is adjusted by selecting a delay signal so that the same timing change is obtained from outputs (6), (16) while varying properly the setting of jumpers of setting circuits 14a, 14b. That is, suppose that the outputs (6), (16) are in the same timing change, then resultingly, a signal (1) is selected as a delay signal of the LSI 11a and a signal (12) is selected. as a delay signal of the LSl 11b. The output (1) of the LSI 11a is delayed while it reaches an output terminal 15a from a selection circuit 13a and the output (12) of the LSI 11b is delayed while it reaches the output terminal from a selection circuit 13b, resulting that the timings are made coincident. Thus, the fine adjustment of clock skew caused by dispersion in the manufacture of the LSIs is attained. |
