| 摘要 |
The circuitry for an adaptive antenna array uses a decorrelation network in cascaded stages which follows the principles of our Appln. No. 8316658, GB 2141588, with each node of the network summating two signals. One of these signals is from an antenna array for nodes of the first stage, or from a node of the previous stage depending on which stage of the network is involved, while the other signal is common to that stage (e.g. from PD1). The first such common input (PD1) comes from one antenna array and at each node one input is inverted with respect to the other to effect decorrelation. At each node one input is weighted (W11, W12, W13, etc) and the weights used are continuously updated using a processor which operates in time shared manner, and which samples the output of each node of each stage (Y1 Y2 Y3 Y4 Z1 Z2 Z3). <IMAGE> |
