Arithmetic processor using redundant signed digit arithmetic

摘要

A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation. The sign of an internal operand is either inverted or the internal operand is converted to 0 in accordance with the value of a control signal and then provided as the internal operand for processing in the first step arithmetic operation. Such sign inversion or conversion of the operand to zero enables the first and second step arithmetic operations to be performed utilizing addition and/or subtraction only.