Vector register file

摘要

A vector register file uses static random access memories organized in a plurality of banks to provide a logical multi-ported vector register file. Each of the four banks may be addressed independently during the same clock cycle. Further, the vector register file is divided into a plurality of context areas, each context area usable by a separate process. Use of a plurality of context areas avoids problems of swapping context data into and out of the vector register file. The method for addressing the vector register file allows for optional addressability to individual cells of the vector register file.