发明名称 TIMING GENERATOR IN SERIAL COMMUNICATION
摘要 PURPOSE:To attain sure timing synchronization without the provision of an exclusive synchronizing signal line by detecting the head of a sent serial data at the reception side and forming a timing signal synchronously therewith after the data is transmitted within a prescribed period. CONSTITUTION:A serial data outputted from an NC device 1 is sent to a communication line 2 from a driver 15. A timing generator consists of a start bit detection section 34 connecting to a receiver 31 at the reception side, a mode setting section 35 setting a synchronizing signal detection mode based on an output of a parallel data from a converter 32, a flip-flop 36 and an AND gate 37. The detection section 34 outputs a detection pulse corresponding to the head of the serial data in one-frame. The flip-flop 36 sets the time range of detect the timing signal at the reception side by using a setting pulse. The AND gate 37 forms a timing signal synchronously with the detection pulse from the detection 34 corresponding to the frame set next to the frame including a synchronizing command.
申请公布号 JPH01245732(A) 申请公布日期 1989.09.29
申请号 JP19880073651 申请日期 1988.03.28
申请人 FANUC LTD 发明人 KATAOKA MINORU;KUMAKURA TATSURO
分类号 H04L7/04 主分类号 H04L7/04
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