| 摘要 |
<p>PURPOSE:To always make equal the phases of a data signal and a clock signal and to output them by providing a head pulse signal generating circuit to generate a pulse signal which shows the head of an input data signal. CONSTITUTION:A head pulse signal 103 which is the output of a head pulse signal generating circuit 3 and a data clock signal 101 extracted from an input data signal 100 by a clock component extracting circuit 1 are sent to a data clock frequency dividing flip flop 4. The flip flop 4 resets and frequency-divides the signal 101 by the signal 103 and generates a clock signal 104 almost synchronous with the phase of the input data 100. A flip flop 5 receives the input data signal 100 and the clock signal 104, synchronizes the phase of the signal 100 with the signal 104 and thus, generates an output data signal 105. Thus, the phases can be controlled so that the phases of the clock signal 101 and the output data signal 105 may be always equal.</p> |
