| 摘要 |
PURPOSE:To narrow a wiring width without reducing a cross-sectional area of a wiring part and to reduce a cell size by a method wherein the wiring part, concerned with an identical signal, to be arranged and installed on a semiconductor region, such as a word line arranged and installed in a high- density memory array part, is made to be a double structure. CONSTITUTION:A piece of information of a memory cell M-Cell 1 is retained by a flip-flop circuit constituted of the following: multiemitter Tr's q1, q2; load resistances r1, r2; Schottky barrier diodes d1, d2; capacitors C1, C2. The cell 1 is connected to signal lines (a word line W100, a data line D, an inverted D and the like). Word lines for said cell 1 and the like are constituted to be a double structure, e.g., a parallel connection of the W100 and a W200. By this setup, since a wiring width can be narrowed without reducing a cross-sectional area of a wiring part, it is possible to reduce a chip size in a large-scale semiconductor integrated circuit. |
