High data bandwidth synchronous interconnect bus structure protocol.

摘要

A modularly expandable computing system having a high bandwidth data bus structure including a high-speed synchronous interconnecting bus (52) and a corresponding signal protocol. The bus, protocol and system provide the maximum process data transfer of contiguous sequences of 8, 32-bit data word which can be transferred from a bus master (54) to a slave device (54) in sequence of two data frames, wherein address and control information of the first frame is overlapped with the data transfer provided in a second frame of a previously addressed data transfer device.