发明名称 PARALLEL ERROR COUNTER CIRCUIT
摘要 PURPOSE:To save number of IC basic logic gates by applying one side error count means for the count of an error bit generating singly and counting the error bit generating simultaneously by a simultaneous error count means and counting the total error by logic calculation. CONSTITUTION:If an error bit takes place only at one side, an output of an OR circuit 50 changes to L and a one-side error counter 10a is counted. When the input of the OR circuit 60 changes to L simultaneously, the simultaneous error counter circuit 20a makes count. Then in order to count each state of the one-side error counter circuit 10a and the simultaneous error counter circuit 20a as the total error bit number for the output NANDing them by NAND circuits 30(1)-30(8), the NAND circuit 31 NANDs the result. Thus, the IC basic logic gates required to constitute the parallel error counter circuit based on ring counters in this way are nearly a half the IC basic logic gate number based on shift registers.
申请公布号 JPH01238317(A) 申请公布日期 1989.09.22
申请号 JP19880066203 申请日期 1988.03.18
申请人 FUJITSU LTD 发明人 SUDA YUKIO;NOZAWA AKIRA
分类号 H03K21/40;H04L1/00 主分类号 H03K21/40
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