| 摘要 |
The circuit for driving the I/O bus with the driving power of the data input buffer (10) during a write cycle when testing includes the first (11) and the second (12) data buses, the first (13) and the second (14) I/O buses, the first (31) and the second (32) lines connected to the data buses, the first (100) and the second (200) transmission gates providing the data of the data buses to the lines at the first clock (&phgr;WDT) of the writing period, the first (300) and the second (400) I/O bus pull-up/down circuits, and an I/O bus equalizing circuit (500) for equalizing I/O buses with the first clock and the equalizing clock.
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