APPARATUS FOR SELECTING BLOCK DECODE COLUMN

摘要

PURPOSE: An apparatus for selecting a block decode column is provided to reduce power consumption by turning on/off a Y-gate transistor of a sense amplifier connected to a column address selection signal according to the selection signal, and by reducing a loading of a main column selection signal. CONSTITUTION: A plurality of sub-column address selectors which output sub-column address selection signals for driving a Y-gate transistor according to a column block selection signal and a main column signal are equipped. The sub-column address selector is composed of a P-MOS transistor, the first N-MOS transistor and the second N-MOS transistor. The P-MOS transistor outputs a main column selection bar signal applied to a source according to the column block selection signal inputted to a gate to a drain. The drain is connected to a drain of the P-MOS transistor. The source is connected to an earth. The gate is connected to a gate of the P-MOS transistor. The first N-MOS transistor is turned on/off according to the column block selection bar signal. The second N-MOS transistor outputs the main column selection signal applied from the drain connected to the source of the P-MOS transistor.