NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To make it possible to transfer reliably a drain voltage necessary at the time of selective writing or readout to a selective cell and to contrive the improvement of the reliability of writing and readout by a method wherein floating gates are contrived so as to cover partially a channel region. CONSTITUTION:4 pieces of memory cells M1-M4 and 2 pieces of selective MOS transistors S1 and S2 are series-connected in the form ot using their sources, drains and diffused layers in common to constitute one NAND cell and the NAND cells are arranged in the form of matrix to constitute a memory array. The drains of each NAND cell are connected to a bit line through the transistor S1. The sources of each NAND cell are connected to a grounding conductor through the transistor S2. Control gates CG1-CG4 of each memory cell are connected to a word line WL which intersects the bit line. Floating gates 4 (41-44) are provided in a state that each one end of the gates does not overlap an element isolation insulating film 2, that is, in a state that the gates 4 cover partially a channel region in regard to the direction of its channel width.