发明名称 CMOS LOGIC CIRCUIT
摘要 The circuit includes a P-type depletion transistor whose gate terminal is coupled with a control voltage input terminal through a first inverter; a P-type transistor whose gate terminal is grounded with the control voltage input terminal, connected to the input terminal of a second inverter through a first N-type transistor whose gate terminal is grounded; and a second N-type transistor whose drain terminal is connected to the source terminal of the first N-type transistor through the output terminal of the second invert and a third inverter, and whose gate terminal is connected to that of the P-type transistor through a fourth inverter.
申请公布号 KR950015205(B1) 申请公布日期 1995.12.23
申请号 KR19880014279 申请日期 1988.10.31
申请人 GOLDSTAR ELECTRONICS CO., LTD. 发明人 KIM, SANG - RYONG
分类号 H03K19/00;(IPC1-7):H03K19/00 主分类号 H03K19/00
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