发明名称 MULTI-FRAME SYNCHRONIZING SYSTEM
摘要 PURPOSE:To realize a multi-frame synchronizing system with small circuit scale by writing/reading conversion data into/from a memory when the positions of pattern reference signal coincide in multi-frames. CONSTITUTION:A couple of counters 1 consisting of a free running basic frame counter 11 which is reset whenever clocks for one multi-frame in m-number of basic frames are counted, and a multi-frame counter 12, a synchronous code detection part 2, an offset holding part 3 holding an offset value from the zero value of the discrete value of the counters 1 and a timing generation part 4 are provided. When the positions of the pattern reference code 0 of a synchronous code F in (m) basic frames of the input multi-frame coincide in (n) multi- frames, conversion data D which a serial/parallel conversion part 10 has converted are constituted to be written into and read from the memory 30 with the timing signal which the timing generation part 4 is generated as address. Thus, the synchronous circuit of various multi-frames and a multi-frame conversion circuit after synchronization can be realized with a simple circuit constitution.
申请公布号 JPH01235427(A) 申请公布日期 1989.09.20
申请号 JP19880062171 申请日期 1988.03.16
申请人 FUJITSU LTD 发明人 YAMAZAKI YOSHIKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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