| 摘要 |
PURPOSE:To prevent a surplus delay when a circuit to be tested operates normally, by providing a transfer gate for inputting an external input into an FF through none of auxiliary gates. CONSTITUTION:A logic block having a plurality of functions which is built by combining basic units comprising an FF 102 suited to the operation of a shift register and a plurality of auxiliary gates (NOR gate 104 and EXOR gate 105) arranged on the input side of the FF 102 is provided with transfer gates 109 and 110 for inputting an external input into the FF 102 through none of the auxiliary gates. With such an arrangement, aside from a signal path passing through an auxiliary gate necessary to perform many functions, a signal path is provided to allow direct inputting into FFs and is controlled by a transfer gate free of gate delay, thereby enabling the production of a logic block with little delay. |
