| 摘要 |
PURPOSE:To reduce the scale of a parallel/serial converting circuit and to decrease the power consumption by fetching the output of a shift means at input of the input of a load pulse generating means and converting said output into the serial data in sequence at and after the highest rank bit by means of a transmission clock. CONSTITUTION:The shift value of a shift means 21 is set at (n-m) bits by means of the bit length (m) obtained by decoding the bit length information supplied via a decoding means 23. Then the parallel valid data of (m) bits supplied to the means 21 is shifted to the position of the (m) bit from the most significant bit and applied to a parallel/serial converting means 22. Then the parallel data is converted into the serial data in sequence and transmitted at and after the most significant bit. In such a case, a load pulse is applied to the means 22 from a load pulse generating means 24 when said conversion is carried out up to the (m) bit. Thus the following parallel data is supplied to the means 22 and converted successively into the serial data again at and after the most significant bit. Then the valid data are continuously transmitted. As a result, a 2-sided data memory can be omitted and the scale of a parallel/serial converting circuit is reduced together with decrease of the power consumption. |
