发明名称 LOGIC CIRCUIT
摘要 PURPOSE:To facilitate a fault detection by providing a test clock control pin for inputting forcibly a test use against a master slave flip-flop (MS-FF) element. CONSTITUTION:The title circuit is constituted of a clock control logical part 1, a scan control circuit 2, a test clock control logical part 3 provided with three pieces of input gates 3a, 3b and 3c, an AND gate 4 and an MS-FF 5. Also, one input of the gate 4c and the other inputs of the gates 3a, 3b and 3c are connected to a clock pin 6 and a test clock control pin 8, respectively. In this state, in spite of an output state of the circuit for controlling an applying condition of a regular clock pin, an input of the clock pin of the MS-FF 5 is realized through the pin 8. Accordingly, a fault detection can be facilitated.
申请公布号 JPH01210876(A) 申请公布日期 1989.08.24
申请号 JP19880036576 申请日期 1988.02.18
申请人 HITACHI LTD 发明人 KONO YASUSHI;YOKOYAMA FUJIO
分类号 G01R31/28;G06F1/04;G06F11/22 主分类号 G01R31/28
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