| 摘要 |
PURPOSE:To omit an exclusive transmission line for transmission and reception by adding a data of logical H to the head of the data, holding the level of the final and preceding stages to logic L and starting the conversion after the logic H is detected in the conversion to parallel data. CONSTITUTION:The transmission/reception timing is set according to a sampling clock CLs and a transfer clock CLt in common to the transmission/reception side generated from a transmission side 10 or a reception side 20 by a data transmitter-receiver 30. In case of the conversion to a serial data, a data validity display section 12 adding the data of logic H to the head of the serial data synchronously with the rise of the clock CLs and holding the final and preceding serial data to logic L is provided to the sender side 10. In case of conversion to the parallel data, a data reproduction instructing section 22 detecting the data of logic H and starting the conversion is provided to the reception side 20. A clock control section 8 sets the transmission/reception timing. |
