| 摘要 |
<p>PURPOSE:To shorten a precharging period by providing a control signal generating circuit which charges a data bus line when a clock signal is inputted and stops the charging when a reset signal is inputted. CONSTITUTION:When the output signal B of a timing circuit 10 varies from 1 to 0, an FF4 is set and a precharging control signal appearing at a terminal -Q varies from 1 to 0. Therefore the MOSFET5 of a charging circuit 2 turns on and all bit lines of the data bus line 6 are charged to a power supply potential VDD. Then, a precharging detecting circuit 3 outputs a reset signal D to the FF4. The FF4 is reset by the signal D and the precharging signal at the terminal -Q varies from the logic 0 to 1. The FET5, therefore, turns off to disconnect the circuit 2 and line 6 from each other. When a control signal E and a write control signal K have logic 0 and a write control signal G and a read control signal I have logic 1, a gate circuit 20 is opened to output the memory code of a register 19 to the line 6.</p> |
