发明名称 MEMORY ACCESS SYSTEM
摘要 PURPOSE:To speed up partial write access by reading out memory data only once from a memory for forming a check bit when data are written in the same word twice or more. CONSTITUTION:When a write access request is outputted from a CPU to a storage device 12, an access request address, control information and data are latched and processed and the succeeding access request is successively received from the CPU. When the 2nd access request is a 'WRITE' request, the addresses 42, 41 of the latched 1st and 2nd accesses are compared with each other by a comparator 9. When the addresses 42, 41 are included in the address range of the same processing unit as the compared result, writing data and a check bit are obtained by using memory data read out by the 1st read cycle, the CPU data of the 1st write cycle and the CPU data of the 2nd write cycle. Consequently, at least two access requests to the storage device can be executed only by one access and partial write access can be rapidly executed.
申请公布号 JPH01194046(A) 申请公布日期 1989.08.04
申请号 JP19880017103 申请日期 1988.01.29
申请人 HITACHI LTD;HITACHI VIDEO ENG CO LTD 发明人 YAMAGAMI HAJIME;KOBAYASHI SHIGEO;KOMORI KAZUHIKO;SEKI YUKIHIRO;ITO HIROMICHI;MASUKO ATSUSHI;KOBAYASHI HITOSHI
分类号 G06F12/16 主分类号 G06F12/16
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