| 摘要 |
PURPOSE:To enable a fast function test by controlling an effective clock by a hold control signal. CONSTITUTION:FF circuits 5-7 are so controlled that a tester clock signal from a common clock input terminal 10 becomes effective only by one pulse within one cycle of a test clock when a hold control signal A is inputted with the tester clock from a logical LSI tester as trigger signal and a synchronization hold control signal is outputted from a synchronization circuit 12. With such an arrangement, data for testing can be set for the circuits 5-7 by applying tester clocks by a specified number according to the position of an FF circuit desired to be tested. Then, a hold control signal B is inputted to be supplied to the circuits 5-7 with the synchronization of the circuit 12 so that a clock signal for testing from a terminal 10 becomes effective only by two continuing pulses within one cycle of the tester clocks. This makes the FFs operate only by these two pulses by a clock with the speed the same as an ordinary clock actually used. |
