| 摘要 |
<p>A sample and hold detector arrangement suitable for construction in integrated circuit form as an automatic chroma gain control detector, or a color oscillator AFPC detector, or the like. A wide bandwidth analog multiplier circuit is supplied with an intermittent reference signal and a second signal, the phase or amplitude of which is to be sampled. Pulses produced across the broad-band load are processed by a sample and hold circuit which provides substantially symmetrical bidirectional conduction to a filter capacitor during the sampling interval and a high holding impedance during the remainder of each cycle. A differential switching circuit provides rapid transition between the sample and hold functions.</p> |
