| 摘要 |
PURPOSE:To generate a test pattern for a sequential circuit at a high speed by providing a D algorithm execution means, a gate element input/output characteristic table, and a composite function element input/output characteristic table. CONSTITUTION:The D algorithm execution means 10 is provided with a fault activation processing means 11 which sets a basic D cube for realizing a fault D value at a fault assumption point, a D drive processing means 12 which generates a chain of D cubes for propagating the fault D value of the basic D cube to an observation point, and a coincidence operation processing means 13 which determines the value of a circuit input for realizing the chain of the D cubes. The gate element input/output characteristic table 20 stores input/ output characteristics of gate elements constituting the sequential circuit. The composite function element input/output characteristic table 30 stores input/ output characteristics of composite function elements constituting the sequential circuit. Then, the execution means 10 generates the test pattern for the sequential circuit by referring to the table 30 as well as the table 20 when performing fault activation processing, D drive processing, and coincidence operation processing. |
