| 摘要 |
PURPOSE:To decrease the power consumption at the non-active time by providing the 1st and 2nd inverse circuits constituted by FET and then connecting the capacity between the gate and the source of the load FET in the 2nd inverse circuit. CONSTITUTION:The 1st inverse circuit consisting of FETQ11 and Q12 is provided along with the 2nd inverse circuit comprising FETQ21 and Q22, and capacitor C22 is connected between the gate and the source of load FETQ22 in the 2nd inverse circuit. When timing pulse phi is at a low level, output phi1 features a high level and phi2 features a low level respectively. Thus, no power is consumed by the two inverse circuits. When timing features a high level exceeding the level which is lower than power source VDD by threshold voltage VTH, phi2 features a low level with FETQ21 turned off. And FETQ23 is turned off since its gate is connected to the power source, and the charge at point B does not go away, thus obtaining the function of a high-efficiency bootstrap circuit. Thus, phi2 is turned to a high level. When phi is lowered, the level of point B can be lowered down suddenly through FETQ23. Thus, the power consumption can be decreased. |
