发明名称 DELAY CIRCUIT
摘要 PURPOSE:To reduce manufacturing cost, and to shorten designing time by adding a junction capacitor with variable capacity to a delay gate, and adjusting delay time by controlling the impressed voltage of both ends of this capacitor. CONSTITUTION:By adding the junction capacitor 3 whose capacity can be varied to the delay gates 1, 2, and by changing the voltage of the capacity value control terminal 4 of the junction capacitor 3, the delay time is made adjustable. For instance, when the delay time is required to extend, the capacity is made large by making the voltage to be impressed to the capacitor small. Thus, since the number of the delay gates is never changed, the redoing of wiring, i.e., the change of a mask is unnecessary, and the manufacturing cost is reduced, and in addition, the designing time can be shortened.
申请公布号 JPH01164116(A) 申请公布日期 1989.06.28
申请号 JP19870322287 申请日期 1987.12.19
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 SHIMOTSUHAMA ISAO;TAMAMURA MASAYA;WATABE YOSHIO;OGAWA KAZUMI;DOI TAKEHITO
分类号 H03K5/13;H03K5/133 主分类号 H03K5/13
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