发明名称 VERTICAL TYPE INSULATING GATE TRANSISTOR
摘要 PURPOSE:To decrease the ON resistance of an element, by causing a source electrode having diffusion junction in a vertical type insulating transistor to be constructed by a Schottky barrier junction. CONSTITUTION:A substrate where the epitaxial growth of Si of an n-type layer is performed at the thickness of a couple of mum-a score of mum is provided on an n<+> type Si and p<+> type contact diffusion regions 7 are formed. Then, a gate oxide film 4, a gate electrodes 3 of poly silicon are formed. Although p-type channel diffusion regions 6 are diffused and formed by using a gate structural body as a mask, p-type regions are extended up to below the gate electrodes by making use of crosswise diffusion. Subsequently, SB electrodes 5 of Pt-Si and the like are deposited and formed by using the gate electrodes and a photoresist 10 as masks. Further, a CVD layer 2 is deposited and formed as a layer insulation film by a low temperature CVD process and a source electrode 1 is formed.
申请公布号 JPH01152671(A) 申请公布日期 1989.06.15
申请号 JP19870311579 申请日期 1987.12.09
申请人 FUJITSU LTD 发明人 NAKATANI YASUTAKA;YAMANAKA KAZUO;SUZUKI SHUICHI
分类号 H01L29/78 主分类号 H01L29/78
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